Modern computer architectures typically cache instructions in a dedicated instruction cache and have various mechanisms for loading the cache efficiently. Typically, these mechanisms involve “prefetching” instructions into the cache which are in the next sequential block from where the processor is currently executing. Branching interrupts this flow and history tables are conventionally used to determine the most likely branch to prefetch along. By way of example, reference U.S. Pat. Nos. 5,394,530, 5,317,702, and 5,168,557. These techniques work well for classically written, procedural programs which tend to have reasonable working sets and iterate “inner loops” of densely packed code.
For non-procedural programs, such as object-oriented code, there are many more unconditional branch and link operations which may or may not be iterated. Thus, object-oriented code typically suffers from degraded cache hit ratios and the classical next sequential block prefetch is often ineffective and may result in degradation of performance of the data processing system. An enhanced prefetch mechanism for prefetching instructions is therefore desirable for a processor executing a non-procedural program such as object-oriented code.